Parameters

Symbol

Mini. Value

Max. Value

Unit

Notes

Data output active (logic high level)

t _{DO active}

/

100

ns

Time between CSn falling edge and data output activation

The first data is shifted to the output register

t _{CLK FE}

500

/

ns

The time between the falling edge of CSn and the first falling edge of CLK

Start data output

T _CLK/2

500

/

ns

The rising edge of CLK shifts out 1 bit at a time

Data output is valid

t _{DO valid}

375

394

ns

The time between the rising edge of CLK and the valid data output

Data output is valid

t _{DO tristate}

/

100

ns

The time between the rising edge of CLK and the valid data output

CSn pulse width

t _CSn

500

/

ns

CSn=High level; ready to start the next angle position reading operation

Read frequency

f _CLK

>0

1

MHz

Clock frequency for reading serial data